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AuthorBin Arif, M Saad
AuthorMustafa, Uvais
AuthorSiddique, Marif Daula
AuthorAhmad, Shahbaz
AuthorIqbal, Atif
AuthorAshique, Ratil Hasnat
AuthorAyob, Shahrin bin
Available date2022-03-06T05:21:54Z
Publication Date2021
Publication NameIET Power Electronics
ResourceScopus
ISSN1755-4535
URIhttp://dx.doi.org/10.1049/pel2.12119
URIhttp://hdl.handle.net/10576/27611
AbstractThis paper presents an improved Multi-level Inverter topology utilizing the concept of boosting-capacitor and two DC sources with reduced switches count for generating 17-level output. The topology employs 10 unidirectional switches including one bidirectional switch. Comparison with other recent topologies shows that the proposed topology employs a reduced number of devices and better performance. The topology combines the modularity of H-Bridge with the boosting capacity of the switched capacitor topology. Special care is taken while designing the switching strategy for voltage balancing of the capacitors. The authors also have generalized the topology to produce 'n' level output. Relevant expressions are also formed and reported. Experimental validation, as well as simulation, is performed, and results are verified. Nearest level control is used as the modulation technique.
SponsorThis publication was made possible by Qatar University-Marubeni Concept to Prototype Development Research Grant # [M-CTP-CENG-2020-2] from the Qatar University. The statements made herein are solely the responsibility of the authors. The APC is funded by the Qatar National Library, Qatar.
Languageen
PublisherJohn Wiley and Sons Inc
SubjectBridge circuits
Electric inverters
Bidirectional switch
Boosting capacity
Experimental validations
Modulation techniques
Multilevel inverter
Switched-capacitor topology
Switching strategies
Voltage balancing
Topology
TitleAn improved asymmetrical multi-level inverter topology with boosted output voltage and reduced components count
TypeArticle
Pagination2052-2066
Issue Number12
Volume Number14


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