A neural network algorithm for hardware-software verification
| Author | Rebaiaia, M.L. |
| Author | Jaam, J.M. |
| Author | Hasnah, A.M. |
| Available date | 2024-03-20T01:55:09Z |
| Publication Date | 2003 |
| Publication Name | Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems |
| Resource | Scopus |
| Abstract | Formal verification is the task of proving that a property holds for a model of a design. This paper examines the idea of a Neural Network-based algorithm used to find the set of states that makes a specification valid. The paper addresses a singular approach for those doing theoretical research for the verification of soft programs, and, for hardware designers. The approach of the application of the Artificial Neural Network is not new, but it becomes interesting if one can improve the truth- building efficiency by using some known artifices. Topics described include Integer Linear Programming, Propositional Logic, Model Checking, Satisfiability problems (SAT) and Artificial Neural Networks (ANN). |
| Language | en |
| Publisher | IEEE |
| Subject | Neural networks Software algorithms Neural network hardware Circuits Logic testing Algebra Logic programming Computer science Artificial neural networks Formal verification |
| Type | Conference Paper |
| Pagination | 1332-1335 |
| Volume Number | 3 |
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